As is well known, a number of applications in the electronic field require a regulation of a current in an electric load. In most cases, the electric load current is regulated by means of a power transistor which may be either of an integrated type or a discrete type. The power transistor, in turn, is driven by means of an integrated drive circuit, referred to as a high side driver.
A shift level or translator circuit is usually associated with high side driver circuits for converting a drive signal, being referred to a respective signal ground, to a drive signal which is referred to a signal ground of the integrated drive circuit. A good translator circuit allows signal propagation times to be minimized, and a propagation of a power on/off signal to be substantially symmetrized.
In certain applications, e.g. switching converters, it is especially important that the switching edges of the power transistor be quite small, so as not to impair the converter efficiency. In addition, false switchings of the power transistor may occur because the ground for the drive circuit is coincident with the source terminal of the power transistor, so that, with the potential at the source terminal varying rapidly, the drive signal should be able to move at the same rate.
The state of the art already offers an approach to meeting this requirement. For example, shown in FIG. 1 of the accompanying drawings is a drive circuit 10, according to the prior art, intended for a power transistor M1 of the NMOS type. The circuit 10 is supplied by a voltage Vs of 12 Volts, and provides an output U for driving the control terminal of the power transistor M1. The power transistor M1 is connected between a supply voltage reference Vcc and one end of an electric load 13. This end is coincident with a signal ground reference of the circuit 10 where a potential GND.sub.-- driver is presented.
A translator circuit 11 is associated with the circuit 10 and utilizes two current generators 14 and 15 generating currents I1 and I2, respectively. Specifically, the translator circuit 11 comprises a transistor A of the NMOS type which has its source terminal connected toward a signal ground, through the first generator 14 of the current I1. The drain terminal of the transistor A is connected to an input terminal IN of the drive circuit 10 and to the second generator 15 of the current I2. A signal DRIVE.sub.-- high is applied to this input terminal IN, while a control terminal G of the transistor A receives a signal DRIVE.sub.-- low.
The transistor A basically functions as a switch. With the switch in the open state, the current I1 is zero, and the signal DRIVE.sub.-- high takes a value which equals the combined values of the ground GND.sub.-- driver of the circuit 10 and the voltage Vs.
On the other hand, when the switch A in the closed state, the current I1 is larger than the current I2, and the potential DRIVE.sub.-- high at the input terminal IN matches that GND.sub.-- driver of the ground reference of the circuit 10. In this situation, the power transistor M1 is forced to the `on` state.
While being in many ways advantageous and essentially achieving its objective, this prior approach is still beset with a risk of false switchings. In fact, upon closing the switch A, the power-on information is transmitted to the power transistor M1, thereby causing it to conduct. The potential at the source terminal of the power transistor M1 rises toward the value of the supply voltage Vcc. This change takes place quite rapidly and results in the current I2 being increased, since the current generator 15 is implemented in the form of a current mirror structure 12, as shown in FIG. 2.
The current mirror 12 comprises a pair of transistors, Ma and Mb, of the PMOS type having their respective control terminals connected together. The transistor Ma is in diode configuration. The dimensional ratios between the transistors Ma and Mb are governed by a parameter k of proportionality, with the dimensions of Mb being k times those of Ma. The gate terminal of the transistor Ma has a first parasitic capacitance C1 toward the source terminal, and a second capacitance C2 toward ground. Accordingly, as the potential at the source terminals moves very rapidly, the gate-source voltage drop across the transistor Ma increases rapidly with respect to the steady-state value of a quantity given by the capacitive divider C1-C2.
Thus, when the power transistor M1 is turned on, the current I2 will be far above its steady-state value, and may even exceed the value of the current I1. Therefore, the node N is charged up to a potential Vcc+Vs, and the output from the circuit 10 forces the power transistor M1 to the `off` state, causing a false or undesired switching.
The problem might be circumvented by arranging for the gate-source capacitance C1 to be much higher than the gate-ground capacitance C2. However, this would entail integration of large-size capacitors in the semiconductor, and consequently, pose well-recognized problems in terms of circuit area occupation.
Alternatively, the current I1 could be rendered much larger than the current I2; but this method has a serious drawback in that it introduces asymmetry in the propagation times of the power on/off signals for the power transistor M1.
Other possible solutions are based on highly complicated and expensive circuit structures involving the use of memory elements.